Near-Optimal Decoding of Incremental Delta-Sigma ADC Output

This paper presents a nonlinear digital decoder (reconstruction filter) for incremental delta-sigma modulators. This decoder utilizes both the magnitude and pattern information of the modulator output to achieve accurate input estimation. Compared to the conventional linear filters with the same oversampling ratio (OSR), it can improve the converter's signal-to-quantization noise ratio by a few dB to a few 10's of dB with slight thermal noise performance degradation. Using the proposed decoder, the modulator's OSR can be a few times less while achieving the same resolution and data rate, thus minimizing the modulator as well as its peripheral circuits' energy consumption. In this paper, the proposed decoder is optimized for digital implementation, with its function being verified using a modulator prototype. This decoder is mainly designed for dc or near-dc signal conversions and it does not provide frequency notches.

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Published in: IEEE Transactions on Circuits and Systems I: Regular Papers
License: https://creativecommons.org/licenses/by/4.0/
See article on publisher's website: https://dx.doi.org/10.1109/tcsi.2020.3010991